Loopback Architecture for Wafer-Level At-Speed Testing of Embedded HyperTransportŽ Processor Links
نویسندگان
چکیده
We present transceiver serial loopback that enables cost-effective wafer-level at-speed testing of HyperTransportTM (HT) I/O for processor die-to-die communication. Besides facilitating known-good-die testing, this feature provides observability of multi-chip module (MCM) die-to-die links that are completely embedded without external pin visibility. We demonstrate production screening of 45-nm SOI-CMOS wafers at 6.4 Gb/s.
منابع مشابه
Embedded Memory Test Strategies and Repair
The demand of self-testing proportionally increases with memory size in System on Chip (SoC). SoC architecture normally occupies the majority of its area by memories. Due to increase in density of embedded memories, there is a need of self-testing mechanism in SoC design. Therefore, this research study focuses on this problem and introduces a smooth solution for self-testing. In the proposed m...
متن کاملLoopback or not?
Issues in design verification of high-speed serial I/O devices. The increasing data rate of high-speed I/O devices makes currently available measurement tools such as realtime oscilloscopes obsolete. Measuring jitter performance of prototyped physical layer ICs of 5 Gb/s will particularly become a critical problem using current-mainstream oscilloscope technology. Therefore, the architecture of ...
متن کاملAC IO Loopback Design for High Speed µProcessor IO Test
This paper presents the next generation AC IO Loopback design for two Intel processor architectures. Both designs detect I/O defects with 20 ps resolution and 50 ps jitter for up to 800 MHz bus speed. Even though the implementations differ in some aspects to accommodate two different bus architectures, the same prudent considerations for high speed operation, minimum test inaccuracy, and low im...
متن کاملA Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores
We have introduced a low-cost at-speed BIST architecture that enables conventional microprocessors and DSP cores to test their functional blocks and embedded SRAMs in system-on-a-chip architectures using their existing hardware and software resources. To accommodate our proposed new test methodology, minor modifications should be applied to base processor within its test phase. That is, we modi...
متن کاملEffective Software-Based Self-Testing for CMOS VLSI Processors
Processor testing approaches based on the execution of self-test programs have been recently proposed as an effective alternative to classic external tester-based testing and pure hardware built-in self-test (BIST) approaches. Software-based self-testing is a non-intrusive testing approach that embeds a “software tester” in the form of a self-test program in the processor on-chip memory. It has...
متن کامل